I. Field of the Invention
The present invention relates to a semiconductor device comprising two transistors having primary current paths connected in series with one another to conduct a primary current through those primary current paths upon receipt of a control signal.
II. Background of the Invention
FIG. 1 illustrates an example of a prior art semiconductor device. The device of FIG. 1 comprises a main bipolar transistor Q1, a field effect transistor (FET) Q2, a zener diode ZD1 and a secondary current source comprising a resistor R1 and a voltage supply E.sub.B. As shown in FIG. 1, the emitter of transistor Q1 is connected to the drain of transistor Q2 to thereby couple the primary (collector/emitter) current path of transistor Q1 in series with the primary (drain/source) current path of transistor Q2. The resultant cascade connection of transistors Q1 and Q2 forms an effective composite transistor comprising transistors Q1 and Q2.
As is further shown in FIG. 1, one pole of voltage supply E.sub.B is connected to the source of transistor of Q2, while the other pole is connected to the base of transistor Q1 through resistor R1. In addition, the cathode of zener diode ZD1 is connected to the base of transistor Q1 and the anode of zener diode ZD1 is connected to the source of transistor Q2. The gate of transistor Q2 is coupled to receive a control signal e.sub.G.
In operation of the prior art device of FIG. 1, a primary current I.sub.C is applied to the collector of transistor Q1 and passes through the primary (collector/emitter) current path of transistor Q1 and the primary (drain/source) current path of transistor Q2 when both transistors Q1 and Q2 are turned ON. With transistors Q1 and Q2 ON, the primary current I.sub.C may be passed through transistors Q1 and Q2 to a load (not shown) coupled to the source of transistor Q2.
The conduction of transistor Q2 is governed by the state of the control signal e.sub.G applied to the gate of transistor Q2. Control signal e.sub.G is supplied by a drive circuit (not shown) as is well known to those skilled in the art. When control signal e.sub.G is HIGH, transistor Q2 is turned ON. In this condition, a base current IB1 is supplied from voltage supply E.sub.B through resistor R1 to the base of transistor Q1, allowing transistor Q1 to also turn ON. To achieve this result, the value of voltage supply E.sub.B must be sufficiently large to drive transistor Q1 ON as transistor Q2 is turned ON by receipt of control signal e.sub.G.
As transistor Q2 turns ON, the voltage V.sub.DS from the drain to the source of transistor Q2 (plus the base to emitter voltage drop of transistor Q1) drops below the breakdown voltage of zener diode ZD1, permitting all of base current IB1 to pass through the base of transistor Q1. When transistor Q2 is OFF, V.sub.DS is sufficiently high to cause all of base current IB1 to be shunted from power supply E.sub.B, through zener diode Z1D, away from the base of transistor Q1. However, the base current IB1 to transistor Q1 rises sharply as transistor Q2 is turned ON due to the steep drop of voltage V.sub.DS, and consequent non-conductance of diode Z1D, when transistor Q2 turns ON. With transistor Q2 ON, zener diode Z1D is in the OFF (non-conductive) state.
Transistors Q1 and Q2 can be turned OFF using the following process. When control signal e.sub.G is LOW, transistor Q2 is turned OFF. Since transistor Q2 is preferably a field effect transistor (FET), transistor Q2 turns OFF quickly, causing voltage V.sub.DS between the drain and source of transistor Q2 to rise quickly, thereby quickly turning OFF the primary current I.sub.C flowing through transistor Q2. At the same time V.sub.DS rises, zener diode ZD1 becomes conductive, thereby shunting secondary or base current IB1 from the base of transistor Q1, through zener diode ZD1, to the source of transistor Q2. With this shunting of base current, accumulated carriers at the base of transister Q1 are rapidly dissipated to the source of transistor Q2, thereby rapidly turning OFF transistor Q1. As a consequence, both transistors Q1 and Q2 are rapidly turned OFF, thereby ceasing conduction of primary current IC through transistors Q1 and Q2.
The circuit of FIG. 1 is generally intended to obtain high switching speed with high voltage resistance by combining a switching element of high speed, low voltage resistance in the form of FET Q2 and a switching element of high voltage resistance in the form of bipolar transistor Q1. Although the switching speed of FET Q2 is generally greater than that of bipolar transistor Q1, the arrangement of FIG. 2 allows transistor Q1 to also be turned OFF rapidly.
In the circuit of FIG. 1, the zener diode ZD1 is operative because the voltage V.sub.DS between the drain and source of transistor Q2 (plus the base to emitter voltage drop of transistor Q1) at the precise moment Q2 turns OFF, assumes a higher voltage than the breakdown voltage or limit voltage for turning ON (switching rejection voltage BDVS) zener diode ZD1. Thus, at essentially the precise moment the primary current through transistor Q2 is turned OFF through operation of transistor Q2, the secondary or effective base current to transistor Q1 is shunted from the base of transistor Q1 through zener diode ZD1, thereby also turning transistor Q1 quickly OFF.
With transistors Q1 and Q2 OFF, the secondary or base current from voltage supply E.sub.B is shunted uselessly through zener diode ZD1 to the source of transistor Q2. On the other hand when transistors Q1 and Q2 are turned on, V.sub.DS between the drain and source of FET Q2 (plus the base to emitter voltage drop of transistor Q2) is less than the breakdown or limit voltage for zener diode ZD1 and the secondary or base current from voltage supply E.sub.B is allowed to pass into the base of transistor Q1.
In actual practice of the device of FIG. 1, wiring exists between the emitter of transistor Q1 and the drain of transistor Q2. This wiring exhibits a floating inductance L1 between the emitter E of transistor Q1 and the drain D of transistor Q2. The floating inductance L1 may generate a transitional excess voltage (spike voltage) illustrated by the dotted lines of FIG. 1, resulting in breakdown of transistor Q2. To avoid such breakdown, it is necessary to somewhat delay turning off transistor Q1 until this spike voltage is reduced to a point where breakdown of transistor Q2 can be prevented. However, such delay increases the total switching time of composite transistors Q1, Q2, thereby minimizing the frequency response of the resultant device.
In view of the foregoing, an object of the present invention is to provide a semiconductor device which minimizes the potential negative effect of floating inductance L1.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention.